Generally, shallow trench isolations (STIs) are used to separate and isolate active areas, such as logic planar or FinFET transistors, photo diodes, memory cells and SRAM cells on a semiconductor substrate from each other. The STIs are formed by etching trenches, forming silicon oxide liners in the trenches, overfilling the trenches with a dielectric such as an oxide, and then removing any excess dielectric outside the trenches. This dielectric helps to electrically isolate the active areas from each other. Before the trenches are formed, the semiconductor substrate has undergone ion implantation resulting in large roughness and interstitial defects on a surface of the semiconductor substrate. The formation of the trenches requires a photo mask process and an etching process, both of which often cause rough and defective sidewall and bottom surfaces of the trenches. In addition, the rough and defective surface of the semiconductor substrate will make the sidewall and bottom surfaces of the trenches even worse, thus resulting in poor trench isolations. From a top view of each trench, it can be seen that a boundary line intersected between the trench sidewall and the surface of the semiconductor substrate is zigzag, i.e., the trench has a high line edge roughness (LER), which is induced by the photoresist used in the photo mask process, and becomes important for feature sizes on the order of 100 nm or less.
In some techniques, for producing a trench with a smooth surface, a lining oxide layer conformal to the sidewall and bottom surfaces is formed directly after forming a trench. However, the lining oxide layer is still formed imperfectly due to the high roughness of the sidewall and bottom surfaces, and hence the trench isolation is adversely affected. In addition, a field implantation is further used after the formation of the lining oxide layer. However, the field implantation often causes implant damages to sidewall and bottom surfaces of the trench.
Besides, the photo mask process and the etching process generally have the difficulties in controlling a rounding radius of a top corner of the trench (located between the sidewall of the trench and the surface of the semiconductor substrate) and a rounding radius of a bottom corner of the trench (located between the sidewall and the bottom surface of the trench). Such uncontrollable rounding radiuses are disadvantageous to forming the trench isolations and filling STIs with dielectric films, especially for high aspect ratio trench isolations.